1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method, a semiconductor device manufacturing equipment and a computer readable medium for performing the semiconductor device manufacturing method.
2. Description of the Related Art
Patterns for semiconductor devices are lately becoming finer in size. Chemical amplification resist is used to form a pattern for a semiconductor device. The precision required of resist pattern dimensions is increasing as patterns for semiconductor devices become finer in size. However, various factors cause the dimensions of an actually formed pattern to deviate from its objective dimensions. Factors for the deviation from the objective dimensions include ones originating from machines such as a coater/developer, an exposure unit, and an etcher, and ones originating from processes. The amount of deviation from the objective dimensions may vary even within the same substrate plane depending on the location. Fluctuations in dimensions within the same substrate plane cause individual differences in electric characteristics and other characteristics of the semiconductor device, and can lead to an increased ratio of defective products.
Controlling the temperature in a post-exposure bake (PEB) step is a known way to control the pattern dimensions. The PEB step is a process of heating resist after exposure, and is conducted in order to accelerate the chemical reaction of the resist.
Technologies of controlling the temperature in the PEB step are disclosed in, for example, JP 2006-228816A (hereinafter referred to as Patent Document 1), JP 2006-237260 A (Patent Document 2), JP 2007-110080 A (Patent Document 3), and an article titled “Across-wafer CD Uniformity Control Through Lithography and Etch Process: Experimental Verification” published in Proceedings of SPIE Vol. 6518 65182 C (Non-Patent Document 1).
JP 2007-35777 A (Patent Document 4) describes a semiconductor device manufacturing method that includes an etching condition setting step, a correlation obtaining step, and a feedback processing step in addition to performing a lithography treatment and an etching treatment on a plurality of semiconductor wafers of each of a plurality of lots. In the correlation obtaining step, obtaining a log of an etcher used in the etching treatment and measuring the etching dimensions are executed in order for each semiconductor wafer. In a relational expression creating step, a parameter is chosen from the etcher log to create, for each chosen parameter, a relational expression that represents the correlation between the parameter and etching dimensions. In the feedback processing step, a parameter obtained for each semiconductor wafer is substituted into the above-mentioned relational expression to calculate etching dimensions, and lithography conditions are set for each semiconductor wafer separately based on the thus calculated predicted values.
The following analyses are given by the present invention.
In a semiconductor device manufacturing process, manufacture conditions have to be reviewed if the dimensions of an actually formed pattern deviate from its objective dimensions. It is important in reviewing manufacture conditions to identify which step has caused the occurring deviation from the objective dimensions. However, as mentioned above, various factors can contribute to the deviation of the dimensions of a pattern formed after etching, and identifying the cause of the deviation is difficult.